The peripheral component interconnect (PCI) specification has been widely adopted in conventional computer systems. The PCI specification defines a local bus system, that includes a PCI bus and a PCI controller for regulating access to the bus. The PCI bus may be connected to different peripheral devices via expansion cards and data may be exchanged between the peripheral devices and a central processing unit (CPU) over the PCI bus. The peripheral devices may seek access to memory locations in main memory over the PCI bus by sending requests to a system memory controller. Each such request to access the system memory is sent as part of a memory access transaction in a non-pipelined fashion. In particular, for each memory access transaction, a memory request is sent from a sender over the PCI bus to the system memory controller, and the sender waits on the request until a response is received. This approach has proven to be especially cumbersome for memory intensive applications, such as three-dimensional rendering, that require a great deal of bandwidth. Unfortunately, the PCI bus does not readily facilitate such a great deal of bandwidth. As a result, the PCI bus serves as a substantial bottleneck for quickly rendering three-dimensional images.
In response to the limitations of the PCI specification, Intel Corporation has established the Accelerated Graphics Port (AGP) specification. AGP is a high performance component level interconnect that is designed for use with three-dimensional graphic display applications. The AGP specification identifies an AGP bus and interface requirements for AGP compliant devices. AGP is based upon a set of performance extensions of the PCI specification that provide increased bandwidth to help better facilitate the large memory bandwidth requirements that are necessary for three-dimensional rendering. AGP provides three primary areas of extensions relative to PCI. First, memory read and write operations are pipelined to hide memory access latency. Second, address data is demultiplexed on the bus to enhance bus efficiency and third, AC timing is provided for 133 MHz data transfer rates.